Estoy tratando de implementar el módulo controlador como un FSM utilizando VHDL, a continuación es el código
entity controller is
Port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
ring_k_1 : in STD_LOGIC;
b_n : in STD_LOGIC_vector(3 downto 0);
start : in STD_LOGIC;
STOP : out STD_LOGIC;
LOAD_CMD : out STD_LOGIC;
ADD_CMD : out STD_LOGIC;
BYPASS_CMD : out STD_LOGIC);
end controller;
architecture Behavioral of controller is
--declare states
type state_typ is (IDLE, INIT, TEST, ADD, BYPASS);
signal state : state_typ;
begin
process(reset,clk)
variable i : STD_LOGIC := '0';
begin
if reset = '0' then
state <= IDLE;
else if clk'event and clk = '1' then
case state is
when IDLE =>
if START = '1' then
state <= INIT;
else
state <= IDLE;
end if;
when INIT =>
state <= TEST;
when TEST =>
if ring_k_1 = '1' then
state <= IDLE;
else if ring_k_1 = '0' and b_n(i) = '0' then
state <= BYPASS;
i <= i+1;
else if (ring = '0' and b_n(i) = '1') then
state <= ADD;
i <= i+1;
end if;
end case; --Syntax error near "case".
end if; --end for the clock event
end process; --Syntax error near "process".
STOP <= '1' when state = IDLE else '0';
ADD_CMD <= '1' when state = ADD else '0';
BYPASS_CMD <= '1' when state = BYPASS else '0';
LOAD_CMD <= '1' when state = INIT else '0';
end Behavioral; --Syntax error near "Behavioral"Me da error de sintaxis al compilar. He puesto la descripción del error como un comentario en el código. ¿Puede alguien ayudarme a corregirlo?
Gracias por las aportaciones. Hice la corrección como se sugirió. Ahora ya no me salen esos errores, en cambio me salen otros y los he corregido todos, pero siguen saliendo dos errores más. Abajo está el código modificado
entity controller is
Port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
ring_k_1 : in STD_LOGIC;
b_n : in STD_LOGIC_vector(3 downto 0);
start : in STD_LOGIC;
STOP : out STD_LOGIC;
LOAD_CMD : out STD_LOGIC;
ADD_CMD : out STD_LOGIC;
BYPASS_CMD : out STD_LOGIC);
end controller;
architecture Behavioral of controller is
--declare states
type state_typ is (IDLE, INIT, TEST, ADD, BYPASS);
signal state : state_typ;
begin
process(reset,clk)
variable i : natural := 0;
begin
if reset = '0' then
state <= IDLE;
STOP <= '1';
else if clk'event and clk = '1' then
case state is
when IDLE =>
if START = '1' then
state <= INIT;
STOP <= '1';
else
state <= IDLE;
STOP <= '0';
end if;
when INIT =>
LOAD_CMD <= '1';
state <= TEST;
when TEST =>
if ring_k_1 = '1' then
state <= IDLE;
elsif ring_k_1 = '0' and b_n(i) = '0' then
state <= BYPASS;
BYPASS_CMD <= '1';
i := i+1;
elsif (ring_k_1 = '0' and b_n(i) = '1') then
state <= ADD;
ADD_CMD <= '1';
i := i+1;
end if;
end case;
end if; --end for the clock event
end process; --Syntax error near "process".(error 1)
-- STOP <= '1' when state = IDLE else '0';
-- ADD_CMD <= '1' when state = ADD else '0';
-- BYPASS_CMD <= '1' when state = BYPASS else '0';
-- LOAD_CMD <= '1' when state = INIT else '0';
end Behavioral; --Expecting type void for <behavioral>.(error 2)He escrito error 1 y error2 en el comentario para señalar el error. Por favor, sugiera la corrección ya que soy novato en la codificación vhdl.
Después de una nueva modificación obtengo el siguiente error. Me he rascado mucho la cabeza pero sigue sin funcionar. Aquí está el código modificado y el error es
ERROR:HDLParsers:164 - "D:/programs_xlinx/BZFAD/controller.vhd" Línea 123. error de análisis, PROCESS inesperado, esperando IF
CÓDIGO:
entity controller is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
ring_k_1 : in STD_LOGIC_vector(3 downto 0);
b_n : in STD_LOGIC_vector(3 downto 0);
start : in STD_LOGIC;
STOP : out STD_LOGIC;
LOAD_CMD : out STD_LOGIC;
ADD_CMD : out STD_LOGIC;
BYPASS_CMD : out STD_LOGIC);
end controller;
architecture Behavioral of controller is
--declare states
type state_typ is (IDLE, INIT, TEST, ADD, BYPASS);
signal state : state_typ;
begin
process(reset,clk)
--variable i : natural := 0;
variable i : integer range b_n'RIGHT to b_n'LEFT := b_n'RIGHT; -- 3 downto 0
begin
if reset = '1' then
state <= IDLE;
STOP <= '1';
else if clk'event and clk = '1' then
case state is
when IDLE =>
if START = '1' then
state <= INIT;
else
state <= IDLE;
STOP <= '1';
end if;
when INIT =>
LOAD_CMD <= '1';
state <= TEST;
when TEST =>
if ring_k_1(3) = '1' then
state <= IDLE;
STOP <= '1';
--
elsif ring_k_1(3) = '0' and b_n(i+1) = '0' then
state <= BYPASS;
BYPASS_CMD <= '1';
-- i := i+1;
if i = b_n'LEFT then
i := 0;
else
i:= i + 1;
end if;
elsif (ring_k_1(3) = '0' and b_n(i+1) = '1') then
state <= ADD;
ADD_CMD <= '1';
if i = b_n'LEFT then
i := 0; -- or use i := b_n'RIGHT;
else
i:= i + 1;
end if;
end if;
when BYPASS =>
state <= TEST;
when ADD =>
state <= TEST;
end case;
end if; --end for the clock event
end process;
end Behavioral;
